PIC18F2420/2520/4420/4520
TABLE 1-2:
PIC18F2420/2520 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
SPDIP,
SOIC
Pin Name
Description
Type Type
QFN
MCLR/VPP/RE3
MCLR
1
26
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
I
ST
ST
VPP
RE3
P
I
Programming voltage input.
Digital input.
OSC1/CLKI/RA7
OSC1
9
6
7
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS otherwise.
External clock source input. Always associated with pin
function, OSC1. (See related OSC1/CLKI, OSC2/CLKO
pins.)
I
I
ST
CLKI
CMOS
RA7
I/O
TTL
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
10
Oscillator crystal or clock output.
O
O
—
—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.
CLKO
RA6
I/O
TTL
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39631E-page 12
© 2008 Microchip Technology Inc.
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