PIC18F2420/2520/4420/4520
FIGURE 1-2:
PIC18F4420/4520 (40/44-PIN) BLOCK DIAGRAM
Data Bus<8>
PORTA
Table Pointer<21>
RA0/AN0
RA1/AN1
Data Latch
8
8
inc/dec logic
21
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
OSC2/CLKO(3)/RA6
OSC1/CLKI(3)/RA7
Data Memory
( 3.9 Kbytes )
PCLATH
PCLATU
Address Latch
20
PCU PCH PCL
Program Counter
12
Data Address<12>
PORTB
31-Level Stack
STKPTR
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
4
BSR
12
FSR0
FSR1
FSR2
4
Address Latch
Access
Bank
Program Memory
(16/32 Kbytes)
RB3/AN9/CCP2(1)
RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
12
Data Latch
inc/dec
logic
8
Table Latch
Address
Decode
PORTC
ROM Latch
IR
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
Instruction Bus <16>
RC5/SDO
RC6/TX/CK
RC7/RX/DT
8
State Machine
Control Signals
Instruction
Decode and
Control
PRODH PRODL
8 x 8 Multiply
PORTD
3
8
RD0/PSP0:RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
W
BITOP
8
8
8
Internal
Oscillator
Block
RD7/PSP7/P1D
OSC1(3)
OSC2(3)
T1OSI
Power-up
Timer
8
8
Oscillator
Start-up Timer
ALU<8>
8
INTRC
Oscillator
Power-on
Reset
8 MHz
Oscillator
Watchdog
Timer
T1OSO
PORTE
RE0/RD/AN5
Precision
Band Gap
Reference
Brown-out
Reset
Fail-Safe
RE1/WR/AN6
RE2/CS/AN7
MCLR(2)
VDD, VSS
Single-Supply
Programming
In-Circuit
MCLR/VPP/RE3(2)
Clock Monitor
Debugger
Data
EEPROM
BOR
Timer0
Timer1
MSSP
Timer2
Timer3
HLVD
ADC
10-Bit
Comparator
ECCP1
CCP2
EUSART
Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set.
2: RE3 is only available when MCLR functionality is disabled.
3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 “Oscillator Configurations” for additional information.
© 2008 Microchip Technology Inc.
DS39631E-page 11
MICROCHIP [ MICROCHIP ]
