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PIC18F4520-I/ML 参数 Datasheet PDF下载

PIC18F4520-I/ML图片预览
型号: PIC18F4520-I/ML
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
TABLE 1-1:  
DEVICE FEATURES  
Features  
PIC18F2420  
PIC18F2520  
PIC18F4420  
PIC18F4520  
Operating Frequency  
DC – 40 MHz  
16384  
DC – 40 MHz  
32768  
DC – 40 MHz  
16384  
DC – 40 MHz  
32768  
Program Memory (Bytes)  
Program Memory  
(Instructions)  
8192  
16384  
8192  
16384  
Data Memory (Bytes)  
Data EEPROM Memory (Bytes)  
Interrupt Sources  
768  
1536  
768  
1536  
256  
256  
256  
256  
19  
19  
20  
20  
I/O Ports  
Ports A, B, C, (E)  
Ports A, B, C, (E)  
Ports A, B, C, D, E  
Ports A, B, C, D, E  
Timers  
4
2
0
4
2
0
4
1
1
4
1
1
Capture/Compare/PWM Modules  
Enhanced  
Capture/Compare/PWM Modules  
Serial Communications  
MSSP,  
MSSP,  
MSSP,  
MSSP,  
Enhanced USART  
Enhanced USART  
Enhanced USART  
Enhanced USART  
Parallel Communications (PSP)  
10-Bit Analog-to-Digital Module  
Resets (and Delays)  
No  
No  
Yes  
Yes  
10 Input Channels  
10 Input Channels  
13 Input Channels  
13 Input Channels  
POR, BOR,  
POR, BOR,  
POR, BOR,  
POR, BOR,  
RESETInstruction,  
Stack Full, Stack  
RESETInstruction,  
Stack Full, Stack  
RESETInstruction,  
Stack Full, Stack  
RESETInstruction,  
Stack Full, Stack  
Underflow (PWRT, OST), Underflow (PWRT, OST), Underflow (PWRT, OST), Underflow (PWRT, OST),  
MCLR (optional), WDT  
MCLR (optional), WDT  
MCLR (optional), WDT  
MCLR (optional), WDT  
Programmable  
Yes  
Yes  
Yes  
Yes  
High/Low-Voltage Detect  
Programmable Brown-out Reset  
Instruction Set  
Yes  
Yes  
Yes  
Yes  
75 Instructions;  
83 with Extended  
75 Instructions;  
83 with Extended  
75 Instructions;  
83 with Extended  
75 Instructions;  
83 with Extended  
Instruction Set Enabled  
Instruction Set Enabled  
Instruction Set Enabled  
Instruction Set Enabled  
Packages  
28-Pin SPDIP  
28-Pin SOIC  
28-Pin QFN  
28-Pin SPDIP  
28-Pin SOIC  
28-Pin QFN  
40-Pin PDIP  
44-Pin QFN  
44-Pin TQFP  
40-Pin PDIP  
44-Pin QFN  
44-Pin TQFP  
© 2008 Microchip Technology Inc.  
DS39631E-page 9  
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