PIC18F2480/2580/4480/4580
GOTO
Unconditional Branch
INCF
Increment f
Syntax:
GOTO
k
Syntax:
INCF f {,d {,a}}
Operands:
Operation:
Status Affected:
0 ≤ k ≤ 1048575
k → PC<20:1>
None
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest
Encoding:
Status Affected:
Encoding:
C, DC, N, OV, Z
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
1111
kkk
k kkk
kkkk
kkkk
kkkk
7
0
8
0010
10da
ffff
ffff
k
19
Description:
The contents of register ‘f’ are
Description:
GOTOallows an unconditional branch
anywhere within entire
2-Mbyte memory range. The 20-bit
value ‘k’ is loaded into PC<20:1>. GOTO
is always a two-cycle
instruction.
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Words:
Cycles:
2
2
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’<7:0>,
No
operation
Read literal
‘k’<19:8>,
Write to PC
Words:
Cycles:
1
1
No
operation
No
No
No
operation
operation
operation
Q Cycle Activity:
Q1
Example:
GOTO THERE
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
After Instruction
PC
=
Address (THERE)
Example:
INCF
CNT, 1, 0
Before Instruction
CNT
Z
=
FFh
0
=
=
=
C
?
DC
?
After Instruction
CNT
Z
=
00h
1
=
=
=
C
1
DC
1
DS39637D-page 388
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
