PIC18F2480/2580/4480/4580
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
EQUATION 16-3:
FOSC
FPWM
⎛
⎝
⎞
⎠
log
bits
PWM Resolution (max) =
log(2)
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation.
TABLE 16-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
FFh
10
4
1
1
3Fh
8
1
1Fh
7
1
FFh
10
FFh
10
17h
6.58
Maximum Resolution (bits)
16.4.3
PWM AUTO-SHUTDOWN
(ECCP1 ONLY)
16.4.4
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
The PWM auto-shutdown features of the Enhanced
CCP module are available to ECCP1 in
PIC18F4480/4580 (40/44-pin) devices. The operation
of this feature is discussed in detail in Section 17.4.7
“Enhanced PWM Auto-Shutdown”.
1. Set the PWM period by writing to the PR2
register.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
Auto-shutdown features are not available for CCP1.
3. Make the CCP1 pin an output by clearing the
appropriate TRIS bit.
4. Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
DS39637D-page 174
© 2009 Microchip Technology Inc.
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