PIC18F2480/2580/4480/4580
TABLE 16-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on Page:
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
BOR
55
56
58
58
58
58
58
57
58
58
56
56
56
57
57
57
57
57
57
57
57
57
(3)
RCON
IPR1
IPEN
PSPIP
SBOREN
ADIP
—
RCIP
RCIF
RCIE
—
TXIP
TXIF
TXIE
EEIP
EEIF
EEIE
SSPIP
SSPIF
SSPIE
BCLIP
BCLIF
BCLIE
CCP1IP
CCP1IF
CCP1IE
HLVDIP
HLVDIF
HLVDIE
TMR2IP
TMR2IF
TMR2IE
TMR1IP
TMR1IF
TMR1IE
PIR1
PSPIF
ADIF
PIE1
PSPIE
ADIE
(2)
(2)
(2)
(2)
IPR2
CMIP
TMR3IP ECCP1IP
TMR3IF ECCP1IF
TMR3IE ECCP1IE
OSCFIP
OSCFIF
OSCFIE
(2)
PIR2
CMIF
—
(2)
PIE2
CMIE
—
TRISB
TRISC
TMR1L
TMR1H
T1CON
TMR3H
TMR3L
T3CON
CCPR1L
CCPR1H
CCP1CON
PORTB Data Direction Register
PORTC Data Direction Register
Timer1 Register Low Byte
Timer1 Register High Byte
RD16
T1RUN
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Timer3 Register High Byte
Timer3 Register Low Byte
(1)
(1)
RD16
T3ECCP1
T3CKPS1 T3CKPS0 T3CCP1
T3SYNC TMR3CS TMR3ON
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
—
—
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1
CCP1M0
(1)
ECCPR1L
ECCPR1H
Enhanced Capture/Compare/PWM Register 1 Low Byte
Enhanced Capture/Compare/PWM Register 1 High Byte
(1)
(1)
ECCP1CON EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by capture, compare, Timer1 or Timer3.
Note 1: These bits or registers are available on PIC18F4X80 devices only.
2: These bits are available on PIC18F4X80 devices and reserved on PIC18F2X80 devices.
3: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See
Section 5.4 “Brown-out Reset (BOR)”.
DS39637D-page 172
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
