PIC18F2480/2580/4480/4580
FIGURE 16-4:
PWM OUTPUT
16.4 PWM Mode
Period
In Pulse-Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with a PORTB or PORTC
data latch, the appropriate TRIS bit must be cleared to
make the CCP1 pin an output.
Duty Cycle
TMR2 = PR2
Note:
Clearing the CCP1CON register will force
the RC2 output latch (depending on
device configuration) to the default low
level. This is not the PORTC I/O data
latch.
TMR2 = Duty Cycle
TMR2 = PR2
16.4.1
PWM PERIOD
Figure 16-3 shows a simplified block diagram of the
CCP module in PWM mode.
The PWM period is specified by writing to the PR2
(PR4) register. The PWM period can be calculated
using the following formula.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 16.4.4
“Setup for PWM Operation”.
EQUATION 16-1:
PWM Period = (PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
FIGURE 16-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
PWM frequency is defined as 1/[PWM period].
CCP1CON<5:4>
Duty Cycle Registers
When TMR1 (TMR3) is equal to PR2 (PR2), the
following three events occur on the next increment
cycle:
CCPR1L
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
CCPR1H (Slave)
Comparator
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Q
R
S
RC2/CCP1
PORTC<2>
Note:
The Timer2 postscalers (see Section 14.0
“Timer2 Module”) are not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
(Note 1)
TMR2
TRISC<2>
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
16.4.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> bits contain
the two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time.
Note 1: The 8-bit TMR2 value is concatenated with 2-bit
internal Q clock, or 2 bits of the prescaler, to create the
10-bit time base.
A PWM output (Figure 16-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
EQUATION 16-2:
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 Prescale Value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
© 2009 Microchip Technology Inc.
DS39637D-page 173
MICROCHIP [ MICROCHIP ]
