PIC18F2480/2580/4480/4580
16.3.2
TIMER1/TIMER3 MODE SELECTION
16.3 Compare Mode
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP1
pin can be:
• driven high
16.3.3
SOFTWARE INTERRUPT MODE
• driven low
When the Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the CCP1 pin is not affected.
Only a CCP interrupt is generated, if enabled, and the
CCP1IE bit is set.
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
I/O latch)
The action on the pin is based on the value of the mode
select bits (ECCP1M<3:0>). At the same time, the
interrupt flag bit, ECCP1IF, is set.
16.3.4
SPECIAL EVENT TRIGGER
Both CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event
(CCP1M<3:0> = 1011).
16.3.1
CCP PIN CONFIGURATION
The user must configure the CCP1 pin as an output by
clearing the appropriate TRIS bit.
Trigger
mode
Note:
Clearing the CCP1CON register will force
the RC2 compare output latch (depending
on device configuration) to the default low
level. This is not the PORTC I/O data
latch.
For either CCP module, the Special Event Trigger
resets the Timer register pair for whichever timer
resource is currently assigned as the module’s time
base. This allows the CCPR1 registers to serve as a
programmable period register for either timer.
FIGURE 16-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger
(Timer1 Reset)
Set CCP1IF
CCPR1H
CCPR1L
CCP1 pin
S
R
Q
Output
Logic
Compare
Match
Comparator
TRIS
Output Enable
4
CCP1CON<3:0>
TMR1H
TMR3H
TMR1L
TMR3L
0
0
1
1
Special Event Trigger
(Timer1/Timer3 Reset, A/D Trigger)
T3CCP1
T3ECCP1
Set CCP1IF
ECCP1 pin
S
R
Q
Compare
Match
Output
Logic
Comparator
TRIS
Output Enable
4
ECCPR1H ECCPR1L
ECCP1CON<3:0>
© 2009 Microchip Technology Inc.
DS39637D-page 171
MICROCHIP [ MICROCHIP ]
