PIC18F2480/2580/4480/4580
TABLE 11-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
PORTA
RA7(1)
RA6(1)
RA5
RA4
RA3
RA2
RA1
RA0
58
58
58
56
57
LATA
LATA7(1) LATA6(1) LATA Output Latch Register
TRISA7(1) TRISA6(1) PORTA Data Direction Register
TRISA
ADCON1
CVRCON(2)
—
—
VCFG1
CVRR
VCFG0
CVRSS
PCFG3
CVR3
PCFG2
CVR2
PCFG1
CVR1
PCFG0
CVR0
CVREN
CVROE
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: RA<7:6> and their associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
2: These registers are unimplemented on PIC18F2X80 devices.
© 2009 Microchip Technology Inc.
DS39637D-page 137