欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F4520-I/PT 参数 Datasheet PDF下载

PIC18F4520-I/PT图片预览
型号: PIC18F4520-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F4520-I/PT的Datasheet PDF文件第193页浏览型号PIC18F4520-I/PT的Datasheet PDF文件第194页浏览型号PIC18F4520-I/PT的Datasheet PDF文件第195页浏览型号PIC18F4520-I/PT的Datasheet PDF文件第196页浏览型号PIC18F4520-I/PT的Datasheet PDF文件第198页浏览型号PIC18F4520-I/PT的Datasheet PDF文件第199页浏览型号PIC18F4520-I/PT的Datasheet PDF文件第200页浏览型号PIC18F4520-I/PT的Datasheet PDF文件第201页  
PIC18F2420/2520/4420/4520  
17.4.14 SLEEP OPERATION  
17.4.17 MULTI -MASTER COMMUNICATION,  
While in Sleep mode, the I2C module can receive  
addresses or data and when an address match or  
complete byte transfer occurs, wake the processor  
from Sleep (if the MSSP interrupt is enabled).  
BUS COLLISION AND BUS  
ARBITRATION  
Multi-Master mode support is achieved by bus arbitra-  
tion. When the master outputs address/data bits onto  
the SDA pin, arbitration takes place when the master  
outputs a ‘1’ on SDA by letting SDA float high and  
another master asserts a ‘0’. When the SCL pin floats  
high, data should be stable. If the expected data on  
SDA is a ‘1’ and the data sampled on the SDA pin = 0,  
then a bus collision has taken place. The master will set  
the Bus Collision Interrupt Flag, BCLIF and reset the  
I2C port to its Idle state (Figure 17-25).  
17.4.15 EFFECTS OF A RESET  
A Reset disables the MSSP module and terminates the  
current transfer.  
17.4.16 MULTI-MASTER MODE  
In Multi-Master mode, the interrupt generation on the  
detection of the Start and Stop conditions allows the  
determination of when the bus is free. The Stop (P) and  
Start (S) bits are cleared from a Reset or when the  
MSSP module is disabled. Control of the I2C bus may  
be taken when the P bit (SSPSTAT<4>) is set, or the  
bus is Idle, with both the S and P bits clear. When the  
bus is busy, enabling the MSSP interrupt will generate  
the interrupt when the Stop condition occurs.  
If a transmit was in progress when the bus collision  
occurred, the transmission is halted, the BF flag is  
cleared, the SDA and SCL lines are deasserted and the  
SSPBUF can be written to. When the user services the  
bus collision Interrupt Service Routine and if the I2C  
bus is free, the user can resume communication by  
asserting a Start condition.  
In multi-master operation, the SDA line must be  
monitored for arbitration to see if the signal level is the  
expected output level. This check is performed in  
hardware with the result placed in the BCLIF bit.  
If a Start, Repeated Start, Stop or Acknowledge condi-  
tion was in progress when the bus collision occurred, the  
condition is aborted, the SDA and SCL lines are deas-  
serted and the respective control bits in the SSPCON2  
register are cleared. When the user services the bus  
collision Interrupt Service Routine and if the I2C bus is  
free, the user can resume communication by asserting a  
Start condition.  
The states where arbitration can be lost are:  
• Address Transfer  
• Data Transfer  
• A Start Condition  
The master will continue to monitor the SDA and SCL  
pins. If a Stop condition occurs, the SSPIF bit will be set.  
• A Repeated Start Condition  
• An Acknowledge Condition  
A write to the SSPBUF will start the transmission of  
data at the first data bit, regardless of where the  
transmitter left off when the bus collision occurred.  
In Multi-Master mode, the interrupt generation on the  
detection of Start and Stop conditions allows the deter-  
mination of when the bus is free. Control of the I2C bus  
can be taken when the P bit is set in the SSPSTAT  
register, or the bus is Idle and the S and P bits are  
cleared.  
FIGURE 17-25:  
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE  
Sample SDA. While SCL is high,  
data doesn’t match what is driven  
by the master.  
Data changes  
while SCL = 0  
SDA line pulled low  
by another source  
Bus collision has occurred.  
SDA released  
by master  
SDA  
SCL  
Set bus collision  
interrupt (BCLIF)  
BCLIF  
© 2008 Microchip Technology Inc.  
DS39631E-page 195