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PIC18F4520-I/PT 参数 Datasheet PDF下载

PIC18F4520-I/PT图片预览
型号: PIC18F4520-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
17.4.12 ACKNOWLEDGE SEQUENCE  
TIMING  
17.4.13 STOP CONDITION TIMING  
A Stop bit is asserted on the SDA pin at the end of a  
receive/transmit by setting the Stop Sequence Enable  
bit, PEN (SSPCON2<2>). At the end of a receive/  
transmit, the SCL line is held low after the falling edge  
of the ninth clock. When the PEN bit is set, the master  
will assert the SDA line low. When the SDA line is  
sampled low, the Baud Rate Generator is reloaded and  
counts down to 0. When the Baud Rate Generator  
times out, the SCL pin will be brought high and one  
TBRG (Baud Rate Generator rollover count) later, the  
SDA pin will be deasserted. When the SDA pin is  
An Acknowledge sequence is enabled by setting the  
Acknowledge Sequence Enable bit, ACKEN  
(SSPCON2<4>). When this bit is set, the SCL pin is  
pulled low and the contents of the Acknowledge data bit  
are presented on the SDA pin. If the user wishes to gen-  
erate an Acknowledge, then the ACKDT bit should be  
cleared. If not, the user should set the ACKDT bit before  
starting an Acknowledge sequence. The Baud Rate  
Generator then counts for one rollover period (TBRG)  
and the SCL pin is deasserted (pulled high). When the  
SCL pin is sampled high (clock arbitration), the Baud  
Rate Generator counts for TBRG. The SCL pin is then  
pulled low. Following this, the ACKEN bit is automatically  
cleared, the Baud Rate Generator is turned off and the  
MSSP module then goes into Idle mode (Figure 17-23).  
sampled high while SCL is high, the  
(SSPSTAT<4>) is set. A TBRG later, the PEN bit is  
cleared and the SSPIF bit is set (Figure 17-24).  
P
bit  
17.4.13.1 WCOL Status Flag  
If the user writes the SSPBUF when a Stop sequence  
is in progress, then the WCOL bit is set and the con-  
tents of the buffer are unchanged (the write doesn’t  
occur).  
17.4.12.1 WCOL Status Flag  
If the user writes the SSPBUF when an Acknowledge  
sequence is in progress, then WCOL is set and the  
contents of the buffer are unchanged (the write doesn’t  
occur).  
FIGURE 17-23:  
ACKNOWLEDGE SEQUENCE WAVEFORM  
Acknowledge sequence starts here,  
write to SSPCON2  
ACKEN automatically cleared  
ACKEN = 1, ACKDT = 0  
TBRG  
ACK  
TBRG  
SDA  
SCL  
D0  
8
9
SSPIF  
Cleared in  
SSPIF set at  
the end of receive  
software  
Cleared in  
software  
SSPIF set at the end  
of Acknowledge sequence  
Note: TBRG = one Baud Rate Generator period.  
FIGURE 17-24:  
STOP CONDITION RECEIVE OR TRANSMIT MODE  
SCL = 1for TBRG, followed by SDA = 1for TBRG  
after SDA sampled high. P bit (SSPSTAT<4>) is set.  
Write to SSPCON2,  
set PEN  
PEN bit (SSPCON2<2>) is cleared by  
hardware and the SSPIF bit is set  
Falling edge of  
9th clock  
TBRG  
SCL  
SDA  
ACK  
P
TBRG  
TBRG  
TBRG  
SCL brought high after TBRG  
SDA asserted low before rising edge of clock  
to setup Stop condition  
Note: TBRG = one Baud Rate Generator period.  
DS39631E-page 194  
© 2008 Microchip Technology Inc.