PIC18F2420/2520/4420/4520
FIGURE 17-27:
BUS COLLISION DURING START CONDITION (SCL =
0)
SDA =
0,
SCL =
1
T
BRG
T
BRG
SDA
Set SEN, enable Start
sequence if SDA =
1,
SCL =
1
SCL =
0
before SDA =
0,
bus collision occurs. Set BCLIF.
SCL =
0
before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
in software
S
SSPIF
‘0’
‘0’
‘0’
‘0’
SCL
SEN
FIGURE 17-28:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA =
0,
SCL =
1
Set S
Less than T
BRG
T
BRG
Set SSPIF
SDA
SDA pulled low by other master.
Reset BRG and assert SDA.
SCL
S
SCL pulled low after BRG
time-out
Set SEN, enable Start
sequence if SDA =
1,
SCL =
1
SEN
BCLIF
‘0’
S
SSPIF
SDA =
0,
SCL =
1,
set SSPIF
Interrupts cleared
in software
©
2008 Microchip Technology Inc.
DS39631E-page 197