PIC18F2420/2520/4420/4520
The operation of the SBOREN bit and the Reset flag
bits is discussed in more detail in Section 4.1 “RCON
Register”.
9.5
RCON Register
The RCON register contains flag bits which are used to
determine the cause of the last Reset or wake-up from
Idle or Sleep modes. RCON also contains the IPEN bit
which enables interrupt priorities.
REGISTER 9-10: RCON: RESET CONTROL REGISTER
R/W-0
IPEN
R/W-1(1)
U-0
—
R/W-1
RI
R-1
TO
R-1
PD
R/W-0(1)
POR
R/W-0
BOR
SBOREN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
SBOREN: Software BOR Enable bit(1)
For details of bit operation, see Register 4-1.
Unimplemented: Read as ‘0’
bit 5
bit 4
RI: RESETInstruction Flag bit
For details of bit operation, see Register 4-1.
TO: Watchdog Timer Time-out Flag bit
For details of bit operation, see Register 4-1.
PD: Power-Down Detection Flag bit
bit 3
bit 2
bit 1
bit 0
For details of bit operation, see Register 4-1.
POR: Power-on Reset Status bit(1)
For details of bit operation, see Register 4-1.
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-1.
Note 1: Actual Reset values are determined by device configuration and the nature of the device Reset. See
Register 4-1 for additional information.
DS39631E-page 102
© 2008 Microchip Technology Inc.
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