PIC18F2420/2520/4420/4520
REGISTER 9-9:
IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
OSCFIP
bit 7
R/W-1
CMIP
U-0
—
R/W-1
EEIP
R/W-1
BCLIP
R/W-1
R/W-1
R/W-1
HLVDIP
TMR3IP
CCP2IP
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
OSCFIP: Oscillator Fail Interrupt Priority bit
1= High priority
0= Low priority
CMIP: Comparator Interrupt Priority bit
1= High priority
0= Low priority
bit 5
bit 4
Unimplemented: Read as ‘0’
EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit
1= High priority
0= Low priority
bit 3
bit 2
bit 1
bit 0
BCLIP: Bus Collision Interrupt Priority bit
1= High priority
0= Low priority
HLVDIP: High/Low-Voltage Detect Interrupt Priority bit
1= High priority
0= Low priority
TMR3IP: TMR3 Overflow Interrupt Priority bit
1= High priority
0= Low priority
CCP2IP: CCP2 Interrupt Priority bit
1= High priority
0= Low priority
© 2008 Microchip Technology Inc.
DS39631E-page 101
MICROCHIP [ MICROCHIP ]
