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PIC18F4520-I/P 参数 Datasheet PDF下载

PIC18F4520-I/P图片预览
型号: PIC18F4520-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
9.4  
IPR Registers  
The IPR registers contain the individual priority bits for  
the peripheral interrupts. Due to the number of periph-  
eral interrupt sources, there are two Peripheral Interrupt  
Priority registers (IPR1 and IPR2). Using the priority bits  
requires that the Interrupt Priority Enable (IPEN) bit be  
set.  
REGISTER 9-8:  
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1  
R/W-1  
PSPIP(1)  
bit 7  
R/W-1  
ADIP  
R/W-1  
RCIP  
R/W-1  
TXIP  
R/W-1  
SSPIP  
R/W-1  
R/W-1  
R/W-1  
CCP1IP  
TMR2IP  
TMR1IP  
bit 0  
Legend:  
R = Readable bit  
-n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
bit 7  
bit 6  
bit 5  
bit 4  
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1)  
1= High priority  
0= Low priority  
ADIP: A/D Converter Interrupt Priority bit  
1= High priority  
0= Low priority  
RCIP: EUSART Receive Interrupt Priority bit  
1= High priority  
0= Low priority  
TXIP: EUSART Transmit Interrupt Priority bit  
1= High priority  
0= Low priority  
bit 3  
bit 2  
bit 1  
bit 0  
SSPIP: Master Synchronous Serial Port Interrupt Priority bit  
1= High priority  
0= Low priority  
CCP1IP: CCP1 Interrupt Priority bit  
1= High priority  
0= Low priority  
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit  
1= High priority  
0= Low priority  
TMR1IP: TMR1 Overflow Interrupt Priority bit  
1= High priority  
0= Low priority  
Note 1: This bit is unimplemented on 28-pin devices and will read as ‘0’.  
DS39631E-page 100  
© 2008 Microchip Technology Inc.  
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