PIC18F2420/2520/4420/4520
TABLE 10-1: PORTA I/O SUMMARY
TRIS
Setting
I/O
Type
Pin
RA0/AN0
Function
I/O
Description
RA0
0
1
1
O
I
DIG LATA<0> data output; not affected by analog input.
TTL PORTA<0> data input; disabled when analog input enabled.
AN0
RA1
I
ANA A/D input channel 0 and comparator C1- input. Default input
configuration on POR; does not affect digital output.
RA1/AN1
0
1
1
O
I
DIG LATA<1> data output; not affected by analog input.
TTL PORTA<1> data input; disabled when analog input enabled.
AN1
RA2
I
ANA A/D input channel 1 and comparator C2- input. Default input
configuration on POR; does not affect digital output.
RA2/AN2/
VREF-/CVREF
0
1
1
O
I
DIG LATA<2> data output; not affected by analog input. Disabled when
CVREF output enabled.
TTL PORTA<2> data input. Disabled when analog functions enabled;
disabled when CVREF output enabled.
AN2
I
ANA A/D input channel 2 and comparator C2+ input. Default input
configuration on POR; not affected by analog output.
VREF-
1
x
I
ANA A/D and comparator voltage reference low input.
CVREF
O
ANA Comparator voltage reference output. Enabling this feature disables
digital I/O.
RA3/AN3/VREF+
RA3
AN3
0
1
1
O
I
DIG LATA<3> data output; not affected by analog input.
TTL PORTA<3> data input; disabled when analog input enabled.
I
ANA A/D input channel 3 and comparator C1+ input. Default input
configuration on POR.
VREF+
RA4
1
0
1
1
0
0
1
1
1
1
0
0
1
I
O
I
ANA A/D and comparator voltage reference high input.
DIG LATA<4> data output.
RA4/T0CKI/C1OUT
ST
ST
PORTA<4> data input; default configuration on POR.
Timer0 clock input.
T0CKI
C1OUT
RA5
I
O
O
I
DIG Comparator 1 output; takes priority over port data.
DIG LATA<5> data output; not affected by analog input.
TTL PORTA<5> data input; disabled when analog input enabled.
ANA A/D input channel 4. Default configuration on POR.
TTL Slave select input for MSSP module.
RA5/AN4/SS/
HLVDIN/C2OUT
AN4
SS
I
I
HLVDIN
C2OUT
RA6
I
ANA High/Low-Voltage Detect external trip point input.
DIG Comparator 2 output; takes priority over port data.
DIG LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
O
O
I
OSC2/CLKO/RA6
OSC1/CLKI/RA7
TTL PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes
only.
OSC2
CLKO
x
x
O
O
ANA Main oscillator feedback output connection (XT, HS and LP modes).
DIG System cycle clock output (FOSC/4) in RC, INTIO1 and EC Oscillator
modes.
RA7
0
1
x
x
O
I
DIG LATA<7> data output. Disabled in external oscillator modes.
TTL PORTA<7> data input. Disabled in external oscillator modes.
ANA Main oscillator input connection.
OSC1
CLKI
I
I
ANA Main clock input connection.
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
DS39631E-page 106
© 2008 Microchip Technology Inc.
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