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PIC18F4520-I/P 参数 Datasheet PDF下载

PIC18F4520-I/P图片预览
型号: PIC18F4520-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
9.6  
INTx Pin Interrupts  
9.7  
TMR0 Interrupt  
External interrupts on the RB0/INT0, RB1/INT1 and  
RB2/INT2 pins are edge-triggered. If the corresponding  
INTEDGx bit in the INTCON2 register is set (= 1), the  
interrupt is triggered by a rising edge; if the bit is clear,  
the trigger is on the falling edge. When a valid edge  
appears on the RBx/INTx pin, the corresponding flag  
bit, INTxIF, is set. This interrupt can be disabled by  
clearing the corresponding enable bit, INTxIE. Flag bit,  
INTxIF, must be cleared in software in the Interrupt  
Service Routine before re-enabling the interrupt.  
In 8-bit mode (which is the default), an overflow in the  
TMR0 register (FFh 00h) will set flag bit, TMR0IF. In  
16-bit mode, an overflow in the TMR0H:TMR0L regis-  
ter pair (FFFFh 0000h) will set TMR0IF. The interrupt  
can be enabled/disabled by setting/clearing enable bit,  
TMR0IE (INTCON<5>). Interrupt priority for Timer0 is  
determined by the value contained in the interrupt  
priority bit, TMR0IP (INTCON2<2>). See Section 11.0  
“Timer0 Module” for further details on the Timer0  
module.  
All external interrupts (INT0, INT1 and INT2) can wake-  
up the processor from Idle or Sleep modes if bit INTxIE  
was set prior to going into those modes. If the Global  
Interrupt Enable bit, GIE, is set, the processor will  
branch to the interrupt vector following wake-up.  
9.8  
PORTB Interrupt-on-Change  
An input change on PORTB<7:4> sets flag bit, RBIF  
(INTCON<0>). The interrupt can be enabled/disabled  
by setting/clearing enable bit, RBIE (INTCON<3>).  
Interrupt priority for PORTB interrupt-on-change is  
determined by the value contained in the interrupt  
priority bit, RBIP (INTCON2<0>).  
Interrupt priority for INT1 and INT2 is determined by the  
value contained in the Interrupt Priority bits, INT1IP  
(INTCON3<6>) and INT2IP (INTCON3<7>). There  
is no priority bit associated with INT0. It is always a  
high-priority interrupt source.  
9.9  
Context Saving During Interrupts  
During interrupts, the return PC address is saved on  
the stack. Additionally, the WREG, STATUS and BSR  
registers are saved on the Fast Return Stack. If a fast  
return from interrupt is not used (see Section 5.3  
“Data Memory Organization”), the user may need to  
save the WREG, STATUS and BSR registers on entry  
to the Interrupt Service Routine. Depending on the  
user’s application, other registers may also need to be  
saved. Example 9-1 saves and restores the WREG,  
STATUS and BSR registers during an Interrupt Service  
Routine.  
EXAMPLE 9-1:  
SAVING STATUS, WREG AND BSR REGISTERS IN RAM  
MOVWF  
MOVFF  
MOVFF  
;
W_TEMP  
STATUS, STATUS_TEMP  
BSR, BSR_TEMP  
; W_TEMP is in virtual bank  
; STATUS_TEMP located anywhere  
; BSR_TMEP located anywhere  
; USER ISR CODE  
;
MOVFF  
MOVF  
MOVFF  
BSR_TEMP, BSR  
W_TEMP, W  
STATUS_TEMP, STATUS  
; Restore BSR  
; Restore WREG  
; Restore STATUS  
© 2008 Microchip Technology Inc.  
DS39631E-page 103  
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