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PIC18F2450-I/SO 参数 Datasheet PDF下载

PIC18F2450-I/SO图片预览
型号: PIC18F2450-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚,高性能, 12 MIPS ,增强型闪存, USB微控制器采用纳瓦技术 [28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 320 页 / 5591 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2450/4450  
17.6 Operation During Sleep  
17.7 Effects of a Reset  
When enabled, the HLVD circuitry continues to operate  
during Sleep. If the device voltage crosses the trip  
point, the HLVDIF bit will be set and the device will  
wake-up from Sleep. Device execution will continue  
from the interrupt vector address if interrupts have  
been globally enabled.  
A device Reset forces all registers to their Reset state.  
This forces the HLVD module to be turned off.  
TABLE 17-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE  
Reset  
Values  
on page  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
HLVDCON VDIRMAG  
IRVST  
HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0  
50  
49  
51  
51  
51  
INTCON  
PIR2  
GIE/GIEH PEIE/GIEL TMR0IE  
INT0IE  
RBIE  
TMR0IF  
HLVDIF  
HLVDIE  
HLVDIP  
INT0IF  
RBIF  
OSCFIF  
OSCFIE  
OSCFIP  
USBIF  
USBIE  
USBIP  
PIE2  
IPR2  
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module.  
© 2006 Microchip Technology Inc.  
Advance Information  
DS39760A-page 187  
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