PIC18F2450/4450
Programming the Configuration registers is done in a
manner similar to programming the Flash memory. The
WR bit in the EECON1 register starts a self-timed write
to the Configuration register. In normal operation mode,
a TBLWT instruction, with the TBLPTR pointing to the
Configuration register, sets up the address and the
data for the Configuration register write. Setting the WR
bit starts a long write to the Configuration register. The
Configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWTinstruction
can write a ‘1’ or a ‘0’ into the cell. For additional details
on Flash programming, refer to Section 6.5 “Writing
to Flash Program Memory”.
18.1 Configuration Bits
The Configuration bits can be programmed (read as
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh), which
can only be accessed using table reads and table writes.
TABLE 18-1: CONFIGURATION BITS AND DEVICE IDs
Default/
Unprogrammed
Value
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300000h CONFIG1L
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
—
IESO
—
—
FCMEN
—
USBDIV CPUDIV1 CPUDIV0 PLLDIV2 PLLDIV1 PLLDIV0
FOSC3 FOSC2 FOSC1 FOSC0
BORV0 BOREN1 BOREN0 PWRTEN
WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN
--00 0000
00-- 0101
--01 1111
---1 1111
1--- -01-
100- 01-1
---- --11
-1-- ----
---- --11
-11- ----
---- --11
-1-- ----
—
—
VREGEN BORV1
—
—
—
—
300005h CONFIG3H MCLRE
—
—
—
—
BBSIZ
—
LPT1OSC PBADEN
—
STVREN
CP0
(2)
300006h CONFIG4L DEBUG XINST ICPRT
LVP
—
—
CP1
—
300008h CONFIG5L
300009h CONFIG5H
30000Ah CONFIG6L
30000Bh CONFIG6H
30000Ch CONFIG7L
30000Dh CONFIG7H
3FFFFEh DEVID1
—
—
—
CPB
—
—
—
—
—
—
—
—
—
—
—
—
—
WRT1
—
WRT0
—
—
WRTB
—
WRTC
—
—
—
—
—
—
—
—
EBTR1
—
EBTR0
—
—
EBTRB
DEV1
DEV9
—
—
—
—
(1)
DEV2
DEV10
DEV0
DEV8
REV4
DEV7
REV3
DEV6
REV2
DEV5
REV1
DEV4
REV0
DEV3
xxxx xxxx
(1)
3FFFFFh DEVID2
0001 0010
Legend:
x= unknown, u= unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Note 1: See Register 18-13 and Register 18-14 for device ID values. DEVID registers are read-only and cannot be programmed
by the user.
2: Available only on PIC18F4450 devices in 44-pin TQFP packages. Always leave this bit clear in all other devices.
DS39760A-page 190
Advance Information
© 2006 Microchip Technology Inc.
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