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PIC18F2450-I/SO 参数 Datasheet PDF下载

PIC18F2450-I/SO图片预览
型号: PIC18F2450-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚,高性能, 12 MIPS ,增强型闪存, USB微控制器采用纳瓦技术 [28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 320 页 / 5591 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2450/4450  
As with the UIE register, the enable bits only affect the  
propagation of an interrupt condition to the  
microcontroller’s interrupt logic. The flag bits are still  
set by their interrupt conditions, allowing them to be  
polled and serviced without actually generating an  
interrupt.  
14.5.4  
USB ERROR INTERRUPT ENABLE  
REGISTER (UEIE)  
The USB Error Interrupt Enable register (Register 14-10)  
contains the enable bits for each of the USB error  
interrupt sources. Setting any of these bits will enable the  
respective error interrupt source in the UEIR register to  
propagate into the UERR bit at the top level of the  
interrupt logic.  
REGISTER 14-10: UEIE: USB ERROR INTERRUPT ENABLE REGISTER  
R/W-0  
U-0  
U-0  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
PIDEE  
BTSEE  
BTOEE  
DFN8EE  
CRC16EE  
CRC5EE  
bit 7  
bit 0  
Legend:  
R = Readable bit  
-n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
bit 7  
BTSEE: Bit Stuff Error Interrupt Enable bit  
1= Bit stuff error interrupt enabled  
0= Bit stuff error interrupt disabled  
bit 6-5  
bit 4  
Unimplemented: Read as ‘0’  
BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit  
1= Bus turnaround time-out error interrupt enabled  
0= Bus turnaround time-out error interrupt disabled  
bit 3  
bit 2  
bit 1  
bit 0  
DFN8EE: Data Field Size Error Interrupt Enable bit  
1= Data field size error interrupt enabled  
0= Data field size error interrupt disabled  
CRC16EE: CRC16 Failure Interrupt Enable bit  
1= CRC16 failure interrupt enabled  
0= CRC16 failure interrupt disabled  
CRC5EE: CRC5 Host Error Interrupt Enable bit  
1= CRC5 host error interrupt enabled  
0= CRC5 host error interrupt disabled  
PIDEE: PID Check Failure Interrupt Enable bit  
1= PID check failure interrupt enabled  
0= PID check failure interrupt disabled  
© 2006 Microchip Technology Inc.  
Advance Information  
DS39760A-page 147  
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