PIC18F2450/4450
Once an interrupt bit has been set by the SIE, it must
be cleared by software by writing a ‘0’. The flag bits
can also be set in software which can aid in firmware
debugging.
14.5.1
USB INTERRUPT STATUS
REGISTER (UIR)
The USB Interrupt Status register (Register 14-7)
contains the flag bits for each of the USB status
interrupt sources. Each of these sources has a
corresponding interrupt enable bit in the UIE register. All
of the USB status flags are ORed together to generate
the USBIF interrupt flag for the microcontroller’s
interrupt funnel.
REGISTER 14-7: UIR: USB INTERRUPT STATUS REGISTER
U-0
—
R/W-0
SOFIF
R/W-0
R/W-0
IDLEIF(1)
R/W-0
TRNIF(2)
R/W-0
ACTVIF(3)
R-0
UERRIF(4)
R/W-0
STALLIF
URSTIF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
SOFIF: START-OF-FRAME Token Interrupt bit
1= A START-OF-FRAME token received by the SIE
0= No START-OF-FRAME token received by the SIE
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
STALLIF: A STALL Handshake Interrupt bit
1= A STALL handshake was sent by the SIE
0= A STALL handshake has not been sent
IDLEIF: Idle Detect Interrupt bit(1)
1= Idle condition detected (constant Idle state of 3 ms or more)
0= No Idle condition detected
TRNIF: Transaction Complete Interrupt bit(2)
1= Processing of pending transaction is complete; read USTAT register for endpoint information
0= Processing of pending transaction is not complete or no transaction is pending
ACTVIF: Bus Activity Detect Interrupt bit(3)
1= Activity on the D+/D- lines was detected
0= No activity detected on the D+/D- lines
UERRIF: USB Error Condition Interrupt bit(4)
1= An unmasked error condition has occurred
0= No unmasked error condition has occurred.
URSTIF: USB Reset Interrupt bit
1= Valid USB Reset occurred; 00h is loaded into UADDR register
0= No USB Reset has occurred
Note 1: Once an Idle state is detected, the user may want to place the USB module in Suspend mode.
2: Clearing this bit will cause the USTAT FIFO to advance (valid only for IN, OUT and SETUP tokens).
3: This bit is typically unmasked only following the detection of a UIDLE interrupt event.
4: Only error conditions enabled through the UEIE register will set this bit. This bit is a status bit only and
cannot be set or cleared by the user.
DS39760A-page 144
Advance Information
© 2006 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
