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PIC18F2450-I/SO 参数 Datasheet PDF下载

PIC18F2450-I/SO图片预览
型号: PIC18F2450-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚,高性能, 12 MIPS ,增强型闪存, USB微控制器采用纳瓦技术 [28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 320 页 / 5591 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2450/4450  
Figure 14-8 shows the interrupt logic for the USB  
module. There are two layers of interrupt registers in  
the USB module. The top level consists of overall USB  
status interrupts; these are enabled and flagged in the  
UIE and UIR registers, respectively. The second level  
consists of USB error conditions, which are enabled  
and flagged in the UEIR and UEIE registers. An  
interrupt condition in any of these triggers a USB Error  
Interrupt Flag (UERRIF) in the top level.  
14.5 USB Interrupts  
The USB module can generate multiple interrupt  
conditions. To accommodate all of these interrupt  
sources, the module is provided with its own interrupt  
logic structure, similar to that of the microcontroller.  
USB interrupts are enabled with one set of control  
registers and trapped with a separate set of flag regis-  
ters. All sources are funneled into a single USB inter-  
rupt  
request,  
USBIF  
(PIR2<5>),  
in  
the  
Interrupts may be used to trap routine events in a USB  
transaction. Figure 14-9 shows some common events  
within a USB frame and their corresponding interrupts.  
microcontroller’s interrupt logic.  
FIGURE 14-8:  
USB INTERRUPT LOGIC FUNNEL  
Top Level USB Interrupts  
Second Level USB Interrupts  
(USB Status Interrupts)  
(USB Error Conditions)  
UIR (Flag) and UIE (Enable) Registers  
UEIR (Flag) and UEIE (Enable) Registers  
SOFIF  
SOFIE  
BTSEF  
BTSEE  
TRNIF  
TRNIE  
USBIF  
BTOEF  
BTOEE  
IDLEIF  
IDLEIE  
DFN8EF  
DFN8EE  
UERRIF  
UERRIE  
CRC16EF  
CRC16EE  
STALLIF  
STALLIE  
CRC5EF  
CRC5EE  
PIDEF  
PIDEE  
ACTVIF  
ACTVIE  
URSTIF  
URSTIE  
FIGURE 14-9:  
EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS  
To Host  
ACK  
From Host  
From Host  
Data  
Set TRNIF  
Set TRNIF  
Set TRNIF  
SETUPToken  
From Host  
IN Token  
To Host  
Data  
From Host  
ACK  
USB Reset  
URSTIF  
From Host  
From Host  
To Host  
ACK  
START-OF-FRAME  
OUT Token Empty Data  
Transaction  
SOFIF  
Transaction  
Complete  
SOF  
RESET  
Differential Data  
SOF  
SETUP  
DATA  
STATUS  
Control Transfer(1)  
1 ms Frame  
Note 1:  
The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers  
will spread across multiple frames.  
© 2006 Microchip Technology Inc.  
Advance Information  
DS39760A-page 143