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PIC18F2450-I/SO 参数 Datasheet PDF下载

PIC18F2450-I/SO图片预览
型号: PIC18F2450-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚,高性能, 12 MIPS ,增强型闪存, USB微控制器采用纳瓦技术 [28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 320 页 / 5591 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2450/4450  
Clearing the transfer complete flag bit, TRNIF, causes  
the SIE to advance the FIFO. If the next data in the  
FIFO holding register is valid, the SIE will immediately  
reassert the interrupt. If no additional data is present,  
TRNIF will remain clear; USTAT data will no longer be  
reliable.  
14.2.3  
USB STATUS REGISTER (USTAT)  
The USB Status register reports the transaction status  
within the SIE. When the SIE issues a USB transfer  
complete interrupt, USTAT should be read to determine  
the status of the transfer. USTAT contains the transfer  
endpoint number, direction and Ping-Pong Buffer  
Pointer value (if used).  
Note:  
If an endpoint request is received while the  
USTAT FIFO is full, the SIE will  
automatically issue a NAK back to the  
host.  
Note:  
The data in the USB Status register is valid  
only when the TRNIF interrupt flag is  
asserted.  
The USTAT register is actually a read window into a  
four-byte status FIFO, maintained by the SIE. It allows  
the microcontroller to process one transfer while the  
SIE processes additional endpoints (Figure 14-4).  
When the SIE completes using a buffer for reading or  
writing data, it updates the USTAT register. If another  
USB transfer is performed before a transaction  
complete interrupt is serviced, the SIE will store the  
status of the next transfer into the status FIFO.  
FIGURE 14-4:  
USTAT FIFO  
USTAT from SIE  
Clearing TRNIF  
Advances FIFO  
4-byte FIFO  
for USTAT  
Data Bus  
REGISTER 14-3: USTAT: USB STATUS REGISTER  
U-0  
R-x  
R-x  
R-x  
R-x  
R-x  
DIR  
R-x  
PPBI(1)  
U-0  
ENDP3  
ENDP2  
ENDP1  
ENDP0  
bit 7  
bit 0  
Legend:  
R = Readable bit  
-n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
bit 7  
Unimplemented: Read as ‘0’  
bit 6-3  
ENDP3:ENDP0: Encoded Number of Last Endpoint Activity bits  
(represents the number of the BDT updated by the last USB transfer)  
1111= Endpoint 15  
1110= Endpoint 14  
....  
0001= Endpoint 1  
0000= Endpoint 0  
bit 2  
bit 1  
bit 0  
DIR: Last BD Direction Indicator bit  
1= The last transaction was an IN token  
0= The last transaction was an OUT or SETUP token  
PPBI: Ping-Pong BD Pointer Indicator bit(1)  
1= The last transaction was to the Odd BD bank  
0= The last transaction was to the Even BD bank  
Unimplemented: Read as ‘0’  
Note 1: This bit is only valid for endpoints with available Even and Odd BD registers.  
DS39760A-page 134  
Advance Information  
© 2006 Microchip Technology Inc.  
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