PIC18F2450/4450
functions as a digital input only pin; as such, it does not
have TRIS or LAT bits associated with its operation.
Otherwise, it functions as the device’s Master Clear input.
In either configuration, RE3 also functions as the
programming voltage input during programming.
9.5
PORTE, TRISE and LATE
Registers
Depending on the particular PIC18F2450/4450 device
selected, PORTE is implemented in two different ways.
For 40/44-pin devices, PORTE is a 4-bit wide port.
Three pins (RE0/AN5, RE1/AN6 and RE2/AN7) are
individually configurable as inputs or outputs. These
pins have Schmitt Trigger input buffers. When selected
as an analog input, these pins will read as ‘0’s.
Note:
On a Power-on Reset, RE3 is enabled as
digital input only if Master Clear
functionality is disabled.
a
EXAMPLE 9-5:
INITIALIZING PORTE
The corresponding data direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISE bit
(= 0) will make the corresponding PORTE pin an output
(i.e., put the contents of the output latch on the selected
pin).
CLRF
PORTE
LATE
0Ah
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
CLRF
MOVLW
MOVWF
MOVLW
; Configure A/D
ADCON1 ; for digital inputs
03h
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
; Value used to
; initialize data
; direction
; Set RE<0> as inputs
; RE<1> as inputs
; RE<2> as outputs
MOVWF
TRISC
Note:
On a Power-on Reset, RE2:RE0 are
configured as analog inputs.
9.5.1
PORTE IN 28-PIN DEVICES
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
For 28-pin devices, PORTE is only available when
Master Clear functionality is disabled (MCLRE = 0). In
these cases, PORTE is a single bit, input only port
comprised of RE3 only. The pin operates as previously
described.
The fourth pin of PORTE (MCLR/VPP/RE3) is an input
only pin. Its operation is controlled by the MCLRE Config-
uration bit. When selected as a port pin (MCLRE = 0), it
REGISTER 9-1:
PORTE REGISTER
U-0
—
U-0
U-0
—
U-0
—
R/W-x
RE3(1,2)
R/W-0
RE2(3)
R/W-0
RE1(3)
R/W-0
RE0(3)
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
RE3:RE0: PORTE Data Input bits(1,2,3)
Note 1: implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0); otherwise,
read as ‘0’.
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
3: Unimplemented in 28-pin devices; read as ‘0’.
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 109
MICROCHIP [ MICROCHIP ]
