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PIC18F2450-I/SO 参数 Datasheet PDF下载

PIC18F2450-I/SO图片预览
型号: PIC18F2450-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚,高性能, 12 MIPS ,增强型闪存, USB微控制器采用纳瓦技术 [28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 320 页 / 5591 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2450/4450  
TABLE 9-5:  
PORTC I/O SUMMARY  
TRIS  
Setting  
Pin  
Function  
I/O  
I/O Type  
Description  
RC0/T1OSO/  
T1CKI  
RC0  
0
1
x
OUT  
IN  
DIG  
ST  
LATC<0> data output.  
PORTC<0> data input.  
T1OSO  
OUT  
ANA  
Timer1 oscillator output; enabled when Timer1 oscillator enabled.  
Disables digital I/O.  
T1CKI  
RC1  
1
0
1
x
IN  
OUT  
IN  
ST  
DIG  
ST  
Timer1 counter input.  
LATC<1> data output.  
PORTC<1> data input.  
RC1/T1OSI/  
UOE  
T1OSI  
IN  
ANA  
Timer1 oscillator input; enabled when Timer1 oscillator enabled.  
Disables digital I/O.  
UOE  
RC2  
0
0
1
0
1
OUT  
OUT  
IN  
DIG  
DIG  
ST  
External USB transceiver OE output.  
LATC<2> data output.  
RC2/CCP1  
RC4/D-/VM  
PORTC<2> data input.  
CCP1  
OUT  
IN  
DIG  
ST  
CCP1 Compare and PWM output; takes priority over port data.  
CCP1 Capture input.  
(1)  
RC4  
D-  
IN  
TTL  
PORTC<4> data input; disabled when USB module or on-chip  
transceiver is enabled.  
(1)  
OUT  
IN  
XCVR USB bus differential minus line output (internal transceiver).  
XCVR USB bus differential minus line input (internal transceiver).  
(1)  
(1)  
VM  
IN  
TTL  
TTL  
External USB transceiver VM input.  
(1)  
RC5/D+/VP  
RC6/TX/CK  
RC5  
IN  
PORTC<5> data input; disabled when USB module or on-chip  
transceiver is enabled.  
(1)  
D+  
OUT  
IN  
XCVR USB bus differential plus line output (internal transceiver).  
XCVR USB bus differential plus line input (internal transceiver).  
1)  
1)  
VP  
IN  
TTL  
DIG  
ST  
External USB transceiver VP input.  
LATC<6> data output.  
RC6  
0
1
0
OUT  
IN  
PORTC<6> data input.  
TX  
CK  
OUT  
DIG  
Asynchronous serial transmit data output (EUSART module); takes  
priority over port data. User must configure as output.  
0
OUT  
DIG  
Synchronous serial clock output (EUSART module); takes priority  
over port data.  
1
0
1
1
1
1
IN  
OUT  
IN  
ST  
DIG  
ST  
Synchronous serial clock input (EUSART module).  
LATC<7> data output.  
RC7/RX/DT  
RC7  
PORTC<7> data input.  
RX  
DT  
IN  
ST  
Asynchronous serial receive data input (EUSART module).  
Synchronous serial data output (EUSART module).  
OUT  
IN  
DIG  
ST  
Synchronous serial data input (EUSART module). User must  
configure as an input.  
Legend:  
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,  
TTL = TTL Buffer Input, XCVR = USB Transceiver, x= Don’t care (TRIS bit does not affect port direction or is  
overridden for this option)  
Note 1: RC4 and RC5 do not have corresponding TRISC bits. In Port mode, these pins are input only. USB data direction is  
determined by the USB configuration.  
© 2006 Microchip Technology Inc.  
Advance Information  
DS39760A-page 105  
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