PIC18F2450/4450
TABLE 9-9:
Pin
PORTE I/O SUMMARY
TRIS
Function
I/O
I/O Type
Description
Setting
RE0/AN5
RE0
0
1
1
0
1
1
0
1
1
OUT
IN
DIG
ST
LATE<0> data output; not affected by analog input.
PORTE<0> data input; disabled when analog input enabled.
A/D input channel 5; default configuration on POR.
LATE<1> data output; not affected by analog input.
PORTE<1> data input; disabled when analog input enabled.
A/D input channel 6; default configuration on POR.
LATE<2> data output; not affected by analog input.
PORTE<2> data input; disabled when analog input enabled.
A/D input channel 7; default configuration on POR.
AN5
RE1
IN
ANA
DIG
ST
RE1/AN6
RE2/AN7
OUT
IN
AN6
RE2
IN
ANA
DIG
ST
OUT
IN
AN7
RE3
IN
ANA
ST
(1)
MCLR/VPP/
RE3
—
IN
PORTE<3> data input; enabled when MCLRE Configuration bit
is clear.
(1)
MCLR
VPP
IN
IN
ST
External Master Clear input; enabled when MCLRE Configuration bit
is set.
—
(1)
—
ANA
High-voltage detection, used for ICSP™ mode entry detection.
Always available regardless of pin mode.
Legend:
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input.
Note 1: RE3 does not have a corresponding TRISE<3> bit. This pin is always an input regardless of mode.
TABLE 9-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTE
LATE(3)
TRISE(3)
ADCON1
—
—
—
—
—
—
—
—
—
—
—
—
RE3(1,2)
—
RE2(3)
LATE2
TRISE2
PCFG2
RE1(3)
LATE1
TRISE1
PCFG1
RE0(3)
LATE0
TRISE0
PCFG0
51
51
51
50
—
—
—
VCFG1
VCFG0
PCFG3
Legend: — = unimplemented, read as ‘0’
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0); otherwise,
read as ‘0’.
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
3: These registers and/or bits are unimplemented on 28-pin devices.
DS39760A-page 110
Advance Information
© 2006 Microchip Technology Inc.
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