PIC18F2450/4450
Reading the PORTA register reads the status of the
pins; writing to it will write to the port latch.
9.0
I/O PORTS
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
The Data Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register read and write the latched output value for
PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The RA6 pin
is multiplexed with the main oscillator pin; it is enabled
as an oscillator or I/O pin by the selection of the main
oscillator in Configuration Register 1H (see
Section 18.1 “Configuration Bits” for details). When
not used as a port pin, RA6 and its associated TRIS
and LAT bits are read as ‘0’.
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (output latch)
RA4 is also multiplexed with the USB module; it serves
as a receiver input from an external USB transceiver.
For details on configuration of the USB module, see
Section 14.2 “USB Status and Control”.
The Data Latch register (LATA) is useful for read-
modify-write operations on the value driven by the I/O
pins.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 9-1.
Several PORTA pins are multiplexed with analog inputs.
The operation of pins RA5 and RA3:RA0 as A/D
converter inputs is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
Register 1).
FIGURE 9-1:
GENERIC I/O PORT
OPERATION
Note:
On a Power-on Reset, RA5 and RA3:RA0
are configured as analog inputs and read
as ‘0’. RA4 is configured as a digital input.
RD LAT
Data
Bus
D
Q
All other PORTA pins have TTL input levels and full
CMOS output drivers.
I/O pin(1)
WR LAT
or
PORT
CK
Data Latch
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
D
Q
WR TRIS
RD TRIS
CK
TRIS Latch
EXAMPLE 9-1:
INITIALIZING PORTA
; Initialize PORTA by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
Input
Buffer
CLRF
PORTA
LATA
0Fh
CLRF
Q
D
MOVLW
MOVWF
MOVLW
; Configure A/D
EN
EN
ADCON1 ; for digital inputs
RD PORT
0CFh
; Value used to
; initialize data
; direction
Note 1: I/O pins have diode protection to VDD and VSS.
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
9.1
PORTA, TRISA and LATA Registers
PORTA is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISA. Setting
a TRISA bit (= 1) will make the corresponding PORTA
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISA bit (= 0)
will make the corresponding PORTA pin an output (i.e.,
put the contents of the output latch on the selected pin).
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 99
MICROCHIP [ MICROCHIP ]
