PIC18F2450/4450
TABLE 9-1:
Pin
PORTA I/O SUMMARY
TRIS
Function
I/O
I/O Type
Description
Setting
RA0/AN0
RA0
0
1
1
OUT
IN
DIG
TTL
ANA
LATA<0> data output; not affected by analog input.
PORTA<0> data input; disabled when analog input enabled.
AN0
RA1
IN
A/D input channel 0. Default configuration on POR; does not affect
digital output.
RA1/AN1
0
1
1
OUT
IN
DIG
TTL
ANA
LATA<1> data output; not affected by analog input.
PORTA<1> data input; reads ‘0’ on POR.
AN1
RA2
IN
A/D input channel 1. Default configuration on POR; does not affect
digital output.
RA2/AN2/
VREF-
0
1
1
OUT
IN
DIG
TTL
ANA
LATA<2> data output; not affected by analog input.
PORTA<2> data input. Disabled when analog functions enabled.
AN2
IN
A/D input channel 2. Default configuration on POR; not affected by
analog output.
VREF-
RA3
1
0
1
1
1
0
1
1
x
0
1
1
1
x
x
IN
OUT
IN
ANA
DIG
TTL
ANA
ANA
DIG
ST
A/D voltage reference low input.
RA3/AN3/
VREF+
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input enabled.
A/D input channel 3. Default configuration on POR.
A/D voltage reference high input.
AN3
VREF+
RA4
IN
IN
RA4/T0CKI/
RCV
OUT
IN
LATA<4> data output; not affected by analog input.
PORTA<4> data input; disabled when analog input enabled.
Timer0 clock input.
T0CKI
RCV
RA5
IN
ST
IN
TTL
DIG
TTL
ANA
ANA
ANA
DIG
External USB transceiver RCV input.
RA5/AN4/
HLVDIN
OUT
IN
LATA<5> data output; not affected by analog input.
PORTA<5> data input; disabled when analog input enabled.
A/D input channel 4. Default configuration on POR.
High/Low-Voltage Detect external trip point input.
Main oscillator feedback output connection (all XT and HS modes).
AN4
HLVDIN
OSC2
CLKO
IN
IN
OUT
OUT
OSC2/CLKO/
RA6
System cycle clock output (FOSC/4); available in EC, ECPLL and
INTCKO modes.
RA6
0
1
OUT
IN
DIG
TTL
LATA<6> data output. Available only in ECIO, ECPIO and INTIO
modes; otherwise, reads as ‘0’.
PORTA<6> data input. Available only in ECIO, ECPIO and INTIO
modes; otherwise, reads as ‘0’.
Legend:
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option)
TABLE 9-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Reset
Values
on page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTA
LATA
—
—
—
—
—
RA6(1)
LATA6(1)
TRISA6(1) TRISA5
RA5
RA4
RA3
RA2
RA1
RA0
LATA0
TRISA0
PCFG0
—
51
51
51
50
52
LATA5
LATA4
LATA3
TRISA3
PCFG3
LATA2
TRISA2
PCFG2
LATA1
TRISA1
PCFG1
TRISA
ADCON1
UCON
TRISA4
VCFG0
PKTDIS
—
VCFG1
SE0
PPBRST
USBEN RESUME SUSPND
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
DS39760A-page 100
Advance Information
© 2006 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
