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PIC18F2450-I/SO 参数 Datasheet PDF下载

PIC18F2450-I/SO图片预览
型号: PIC18F2450-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚,高性能, 12 MIPS ,增强型闪存, USB微控制器采用纳瓦技术 [28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 320 页 / 5591 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2450/4450  
TABLE 9-3:  
PORTB I/O SUMMARY  
TRIS  
Setting  
Pin  
Function  
I/O  
I/O Type  
Description  
RB0/AN12/  
INT0  
RB0  
0
1
OUT  
IN  
DIG  
TTL  
LATB<0> data output; not affected by analog input.  
PORTB<0> data input; weak pull-up when RBPU bit is cleared.  
(1)  
Disabled when analog input enabled.  
(1)  
AN12  
INT0  
RB1  
1
1
0
1
IN  
IN  
ANA  
ST  
A/D input channel 12.  
External interrupt 0 input.  
RB1/AN10/  
INT1  
OUT  
IN  
DIG  
TTL  
LATB<1> data output; not affected by analog input.  
PORTB<1> data input; weak pull-up when RBPU bit is cleared.  
Disabled when analog input enabled.  
(1)  
(1)  
AN10  
INT1  
RB2  
1
1
0
1
IN  
IN  
ANA  
ST  
A/D input channel 10.  
External interrupt 1 input.  
RB2/AN8/  
INT2/VMO  
OUT  
IN  
DIG  
TTL  
LATB<2> data output; not affected by analog input.  
PORTB<2> data input; weak pull-up when RBPU bit is cleared.  
Disabled when analog input enabled.  
(1)  
(1)  
AN8  
INT2  
VMO  
RB3  
1
1
0
0
1
IN  
IN  
ANA  
ST  
A/D input channel 8.  
External interrupt 2 input.  
OUT  
OUT  
IN  
DIG  
DIG  
TTL  
External USB transceiver VMO data output.  
LATB<3> data output; not affected by analog input.  
PORTB<3> data input; weak pull-up when RBPU bit is cleared.  
RB3/AN9/VPO  
(1)  
Disabled when analog input enabled.  
(1)  
AN9  
VPO  
RB4  
1
0
0
1
IN  
OUT  
OUT  
IN  
ANA  
DIG  
DIG  
TTL  
A/D input channel 9.  
External USB transceiver VPO data output.  
RB4/AN11/  
KBI0  
LATB<4> data output; not affected by analog input.  
PORTB<4> data input; weak pull-up when RBPU bit is cleared.  
Disabled when analog input enabled.  
(1)  
(1)  
AN11  
KBI0  
RB5  
1
1
0
1
1
x
IN  
IN  
ANA  
TTL  
DIG  
TTL  
TTL  
ST  
A/D input channel 11.  
Interrupt-on-pin change.  
RB5/KBI1/  
PGM  
OUT  
IN  
LATB<5> data output.  
PORTB<5> data input; weak pull-up when RBPU bit is cleared.  
Interrupt-on-pin change.  
KBI1  
PGM  
IN  
IN  
Single-Supply Programming mode entry (ICSP™). Enabled by LVP  
Configuration bit; all other pin functions disabled.  
RB6/KBI2/  
PGC  
RB6  
0
1
1
x
0
1
1
x
x
OUT  
IN  
DIG  
TTL  
TTL  
ST  
LATB<6> data output.  
PORTB<6> data input; weak pull-up when RBPU bit is cleared.  
Interrupt-on-pin change.  
KBI2  
PGC  
RB7  
IN  
(2)  
IN  
Serial execution (ICSP) clock input for ICSP and ICD operation.  
RB7/KBI3/  
PGD  
OUT  
IN  
DIG  
TTL  
TTL  
DIG  
ST  
LATB<7> data output.  
PORTB<7> data input; weak pull-up when RBPU bit is cleared.  
Interrupt-on-pin change.  
KBI3  
PGD  
IN  
(2)  
OUT  
IN  
Serial execution data output for ICSP and ICD operation.  
(2)  
Serial execution data input for ICSP and ICD operation.  
Legend:  
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,  
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option)  
Note 1: Configuration on POR is determined by PBADEN Configuration bit. Pins are configured as analog inputs when  
PBADEN is set and digital inputs when PBADEN is cleared.  
2: All other pin functions are disabled when ICSP™ or ICD operation is enabled.  
DS39760A-page 102  
Advance Information  
© 2006 Microchip Technology Inc.  
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