PIC18F2420/2520/4420/4520
FIGURE 26-16:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
bit 6 - - - - - -1
bit 6 - - - -1
LSb
SDO
SDI
75, 76
77
MSb In
74
LSb In
Note: Refer to Figure 26-5 for load conditions.
TABLE 26-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input
TssL2scL
3 TCY
—
ns
71
TscH
TscL
Tb2b
SCK Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
ns
SCK Input Low Time
(Slave mode)
72A
73A
74
ns (Note 1)
ns (Note 2)
ns
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
40
75
TdoR
SDO Data Output Rise Time
PIC18FXXXX
—
25
45
ns
PIC18LFXXXX
—
ns VDD = 2.0V
76
77
80
TdoF
SDO Data Output Fall Time
—
25
ns
TssH2doZ SS ↑ to SDO Output High-Impedance
TscH2doV, SDO Data Output Valid after SCK PIC18FXXXX
10
50
ns
—
50
ns
TscL2doV Edge
PIC18LFXXXX
—
100
50
ns VDD = 2.0V
82
83
TssL2doV SDO Data Output Valid after SS ↓ PIC18FXXXX
—
—
ns
Edge
PIC18LFXXXX
100
—
ns VDD = 2.0V
ns
TscH2ssH, SS ↑ after SCK Edge
TscL2ssH
1.5 TCY + 40
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
DS39631E-page 352
© 2008 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
