PIC18F2420/2520/4420/4520
FIGURE 26-19:
MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS
SCL
SDA
93
91
90
92
Stop
Condition
Start
Condition
Note: Refer to Figure 26-5 for load conditions.
TABLE 26-20: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
90
TSU:STA Start Condition
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for
Repeated Start
condition
91
92
93
THD:STA Start Condition
Hold Time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
ns After this period, the
first clock pulse is
generated
2(TOSC)(BRG + 1)
TSU:STO Stop Condition
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
ns
2(TOSC)(BRG + 1)
THD:STO Stop Condition
Hold Time
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
ns
2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
FIGURE 26-20:
MASTER SSP I2C™ BUS DATA TIMING
103
102
100
101
109
SCL
90
106
91
92
107
SDA
In
110
109
SDA
Out
Note: Refer to Figure 26-5 for load conditions.
© 2008 Microchip Technology Inc.
DS39631E-page 355
MICROCHIP [ MICROCHIP ]
