PIC18F2420/2520/4420/4520
FIGURE 26-15:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
MSb
LSb
SDO
SDI
bit 6 - - - - - -1
77
75, 76
MSb In
74
bit 6 - - - -1
LSb In
73
Note:
Refer to Figure 26-5 for load conditions.
TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input
TssL2scL
3 TCY
—
ns
71
TscH
SCK Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
71A
72
40
ns (Note 1)
TscL
SCK Input Low Time
(Slave mode)
1.25 TCY + 30
ns
72A
73
40
20
ns (Note 1)
TdiV2scH, Setup Time of SDI Data Input to SCK Edge
TdiV2scL
ns
73A
74
Tb2b
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
—
—
ns (Note 2)
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
40
ns
75
TdoR
SDO Data Output Rise Time
PIC18FXXXX
—
25
45
25
50
50
100
—
ns
PIC18LFXXXX
—
ns VDD = 2.0V
76
77
80
TdoF
SDO Data Output Fall Time
—
ns
TssH2doZ SS ↑ to SDO Output High-Impedance
TscH2doV, SDO Data Output Valid after SCK Edge PIC18FXXXX
TscL2doV
10
ns
—
—
ns
PIC18LFXXXX
ns VDD = 2.0V
ns
83
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5 TCY + 40
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
© 2008 Microchip Technology Inc.
DS39631E-page 351
MICROCHIP [ MICROCHIP ]
