PIC18F2420/2520/4420/4520
FIGURE 26-13:
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
bit 6 - - - - - -1
LSb
SDO
SDI
75, 76
MSb In
74
bit 6 - - - -1
LSb In
73
Note: Refer to Figure 26-5 for load conditions.
TABLE 26-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input
TCY
—
—
—
—
ns
TssL2scL
73
TdiV2scH, Setup Time of SDI Data Input to SCK Edge
TdiV2scL
20
ns
73A
74
Tb2b
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40
of Byte 2
ns (Note 2)
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
40
ns
75
TdoR
SDO Data Output Rise Time PIC18FXXXX
PIC18LFXXXX
—
—
—
—
—
—
—
—
25
45
25
25
45
25
50
100
ns
ns VDD = 2.0V
76
78
TdoF
TscR
SDO Data Output Fall Time
ns
SCK Output Rise Time
(Master mode)
PIC18FXXXX
PIC18LFXXXX
ns
ns VDD = 2.0V
79
80
TscF
SCK Output Fall Time (Master mode)
ns
TscH2doV, SDO Data Output Valid after PIC18FXXXX
TscL2doV SCK Edge
ns
PIC18LFXXXX
ns VDD = 2.0V
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
© 2008 Microchip Technology Inc.
DS39631E-page 349
MICROCHIP [ MICROCHIP ]
