PIC18F45J10 FAMILY
REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
R/W-1
CMIP
U-0
—
U-0
—
R/W-1
U-0
—
U-0
—
R/W-0
OSCFIP
BCL1IP
CCP2IP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
OSCFIP: Oscillator Fail Interrupt Priority bit
1= High priority
0= Low priority
CMIP: Comparator Interrupt Priority bit
1= High priority
0= Low priority
bit 5-4
bit 3
Unimplemented: Read as ‘0’
BCL1IP: Bus Collision Interrupt Priority bit (MSSP1 module)
1= High priority
0= Low priority
bit 2-1
bit 0
Unimplemented: Read as ‘0’
CCP2IP: CCP2 Interrupt Priority bit
1= High priority
0= Low priority
REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
R/W-1
R/W-1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
SSP2IP
BCL2IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit
1= High priority
0= Low priority
bit 6
BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module)
1= High priority
0= Low priority
bit 5-0
Unimplemented: Read as ‘0’
© 2009 Microchip Technology Inc.
DS39682E-page 93
MICROCHIP [ MICROCHIP ]
