PIC18F45J10 FAMILY
9.4
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Priority registers (IPR1, IPR2, IPR3). Using
the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
REGISTER 9-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
PSPIP(1)
R/W-1
ADIP
R/W-1
RCIP
R/W-1
TXIP
R/W-1
R/W-1
R/W-1
R/W-1
SSP1IP
CCP1IP
TMR2IP
TMR1IP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1)
1= High priority
0= Low priority
ADIP: A/D Converter Interrupt Priority bit
1= High priority
0= Low priority
RCIP: EUSART Receive Interrupt Priority bit
1= High priority
0= Low priority
TXIP: EUSART Transmit Interrupt Priority bit
1= High priority
0= Low priority
bit 3
bit 2
bit 1
bit 0
SSP1IP: Master Synchronous Serial Port 1 Interrupt Priority bit
1= High priority
0= Low priority
CCP1IP: ECCP1/CCP1 Interrupt Priority bit
1= High priority
0= Low priority
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1= High priority
0= Low priority
TMR1IP: TMR1 Overflow Interrupt Priority bit
1= High priority
0= Low priority
Note 1: This bit is not implemented on 28-pin devices and should be read as ‘0’.
DS39682E-page 92
© 2009 Microchip Technology Inc.
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