PIC18F45J10 FAMILY
9.3
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Enable registers (PIE1, PIE2, PIE3). When
IPEN = 0, the PEIE bit must be set to enable any of
these peripheral interrupts.
REGISTER 9-7:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
PSPIE(1)
bit 7
R/W-0
ADIE
R/W-0
RCIE
R/W-0
TXIE
R/W-0
R/W-0
R/W-0
R/W-0
SSP1IE
CCP1IE
TMR2IE
TMR1IE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
RCIE: EUSART Receive Interrupt Enable bit
1= Enables the EUSART receive interrupt
0= Disables the EUSART receive interrupt
TXIE: EUSART Transmit Interrupt Enable bit
1= Enables the EUSART transmit interrupt
0= Disables the EUSART transmit interrupt
SSP1IE: Master Synchronous Serial Port 1 Interrupt Enable bit
1= Enables the MSSP interrupt
0= Disables the MSSP interrupt
CCP1IE: ECCP1/CCP1 Interrupt Enable bit
1= Enables the ECCP1/CCP1 interrupt
0= Disables the ECCP1/CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Note 1: This bit is not implemented on 28-pin devices and should be read as ‘0’.
DS39682E-page 90
© 2009 Microchip Technology Inc.
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