PIC18F45J10 FAMILY
10.1 I/O Port Pin Capabilities
10.0 I/O PORTS
When developing an application, the capabilities of the
port pins must be considered. Outputs on some pins
have higher output drive strength than others. Similarly,
some pins can tolerate higher than VDD input levels.
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
10.1.1
PIN OUTPUT DRIVE
The output pin drive strengths vary for groups of pins
intended to meet the needs for a variety of applications.
PORTB and PORTC are designed to drive higher
loads, such as LEDs. All other ports are designed for
small loads, typically indication only. Table 10-1 sum-
marizes the output capabilities. Refer to Section 24.0
“Electrical Characteristics” for more details.
Each port has three registers for its operation. These
registers are:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (Data Latch register)
The Data Latch (LAT register) is useful for read-modify-
write operations on the value that the I/O pins are
driving.
TABLE 10-1: OUTPUT DRIVE LEVELS
Port
Drive
Description
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 10-1.
PORTA
PORTD
PORTE
PORTB
PORTC
Minimum Intended for indication.
FIGURE 10-1:
GENERIC I/O PORT
OPERATION
Suitable for direct LED drive
High
levels.
RD LAT
10.1.2
INPUT PINS AND VOLTAGE
CONSIDERATIONS
Data
Bus
D
Q
The voltage tolerance of pins used as device inputs is
dependent on the pin’s input function. Pins that are used
as digital only inputs are able to handle DC voltages up
to 5.5V; a level typical for digital logic circuits. In contrast,
pins that also have analog input functions of any kind
can only tolerate voltages up to VDD. Voltage excursions
beyond VDD on these pins should be avoided. Table 10-
WR LAT
or PORT
I/O pin
CK
Data Latch
D
Q
WR TRIS
RD TRIS
CK
TRIS Latch
2
summarizes the input capabilities. Refer to
Input
Buffer
Section 24.0 “Electrical Characteristics” for more
details.
TABLE 10-2: INPUT VOLTAGE LEVELS
Tolerated
Q
D
Port or Pin
Description
Input
EN
EN
PORTA<5:0>
PORTB<5:0>
PORTC<1:0>
PORTE<2:0>
PORTB<7:6>
PORTC<7:2>
PORTD<7:0>
RD PORT
Only VDD input levels
tolerated.
VDD
Tolerates input levels
above VDD, useful for
most standard logic.
5.5V
© 2009 Microchip Technology Inc.
DS39682E-page 97
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