PIC18F45J10 FAMILY
16.4.6
MASTER MODE
Note:
The MSSP module, when configured in
I2C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register to
initiate transmission before the Start con-
dition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPxBUF did not occur.
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPxCON1 and by setting
the SSPEN bit. In Master mode, the SCLx and SDAx
lines are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I2C bus may be taken when the P bit is
set, or the bus is Idle, with both the S and P bits clear.
The following events will cause the MSSP Interrupt
Flag bit, SSPxIF, to be set (and MSSP interrupt, if
enabled):
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit conditions.
• Start condition
Once Master mode is enabled, the user has six
options.
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
1. Assert a Start condition on SDAx and SCLx.
2. Assert a Repeated Start condition on SDAx and
SCLx.
3. Write to the SSPxBUF register initiating
transmission of data/address.
4. Configure the I2C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDAx and SCLx.
2
FIGURE 16-16:
MSSP BLOCK DIAGRAM (I C™ MASTER MODE)
Internal
Data Bus
SSPM<3:0>
SSPxADD<6:0>
Read
Write
SSPxBUF
SSPxSR
Baud
Rate
Generator
SDAx
Shift
Clock
SDAx In
MSb
LSb
Start bit, Stop bit,
Acknowledge
Generate
SCLx
Start bit Detect,
Stop bit Detect,
Write Collision Detect,
Clock Arbitration,
State Counter for
End of XMIT/RCV
SCLx In
Bus Collision
Set/Reset S, P, WCOL (SSPxSTAT, SSPxCON1);
Set SSPxIF, BCLxIF;
Reset ACKSTAT, PEN (SSPxCON2)
DS39682E-page 176
© 2009 Microchip Technology Inc.
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