PIC18F45J10 FAMILY
Table 16-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD.
16.4.7
BAUD RATE
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPxADD register (Figure 16-17). When a write
occurs to SSPxBUF, the Baud Rate Generator will
automatically begin counting. The BRG counts down to
‘0’ and stops until another reload has taken place. The
BRG count is decremented twice per instruction cycle
(TCY) on the Q2 and Q4 clocks. In I2C Master mode, the
BRG is reloaded automatically.
16.4.7.1
Baud Rate and Module
Interdependence
Because MSSP1 and MSSP2 are independent, they
can operate simultaneously in I2C Master mode at
different baud rates. This is done by using different
BRG reload values for each module.
Because this mode derives its basic clock source from
the system clock, any changes to the clock will affect
both modules in the same proportion. It may be pos-
sible to change one or both baud rates back to a
previous value by changing the BRG reload value.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCLx pin
will remain in its last state.
FIGURE 16-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0>
SSPxADD<6:0>
SSPM<3:0>
SCLx
Reload
Control
Reload
BRG Down Counter
CLKO
FOSC/4
TABLE 16-3: I2C™ CLOCK RATE w/BRG
FSCL
FCY
FCY * 2
BRG Value
(2 Rollovers of BRG)
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
20 MHz
20 MHz
20 MHz
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
18h
1Fh
63h
09h
0Ch
27h
02h
09h
00h
400 kHz(1)
312.5 kHz
100 kHz
400 kHz(1)
308 kHz
100 kHz
333 kHz(1)
100 kHz
1 MHz(1)
Note 1: The I2C™ interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
DS39682E-page 178
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
