PIC18F45J10 FAMILY
16.4.8
I2C MASTER MODE START
CONDITION TIMING
Note:
If, at the beginning of the Start condition,
the SDAx and SCLx pins are already sam-
pled low, or if during the Start condition, the
SCLx line is sampled low before the SDAx
line is driven low, a bus collision occurs.
The Bus Collision Interrupt Flag, BCLxIF,
is set, the Start condition is aborted and
the I2C module is reset into its Idle state.
To initiate a Start condition, the user sets the Start
Enable bit, SEN (SSPxCON2<0>). If the SDAx and
SCLx pins are sampled high, the Baud Rate Generator
is reloaded with the contents of SSPxADD<6:0> and
starts its count. If SCLx and SDAx are both sampled
high when the Baud Rate Generator times out (TBRG),
the SDAx pin is driven low. The action of the SDAx
being driven low while SCLx is high is the Start condi-
tion and causes the S bit (SSPxSTAT<3>) to be set.
Following this, the Baud Rate Generator is reloaded
with the contents of SSPxADD<6:0> and resumes its
count. When the Baud Rate Generator times out
(TBRG), the SEN bit (SSPxCON2<0>) will be automati-
cally cleared by hardware. The Baud Rate Generator is
suspended, leaving the SDAx line held low and the
Start condition is complete.
16.4.8.1
WCOL Status Flag
If the user writes the SSPxBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPxCON2 is disabled until the Start
condition is complete.
FIGURE 16-19:
FIRST START BIT TIMING
Set S bit (SSPxSTAT<3>)
Write to SEN bit occurs here
SDAx = 1,
At completion of Start bit,
hardware clears SEN bit
and sets SSPxIF bit
SCLx = 1
TBRG
TBRG
Write to SSPxBUF occurs here
2nd bit
1st bit
SDAx
TBRG
SCLx
TBRG
S
DS39682E-page 180
© 2009 Microchip Technology Inc.
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