PIC18F45J10 FAMILY
REGISTER 16-2: SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE)
R/W-0
WCOL
R/W-0
SSPOV(1)
R/W-0
SSPEN(2)
R/W-0
CKP
R/W-0
SSPM3(3)
R/W-0
SSPM2(3)
R/W-0
SSPM1(3)
R/W-0
SSPM0(3)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
WCOL: Write Collision Detect bit
1= The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0= No collision
bit 6
SSPOV: Receive Overflow Indicator bit(1)
SPI Slave mode:
1= A new byte is received while the SSPxBUF register is still holding the previous data. In case of
overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read
the SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in
software).
0= No overflow
bit 5
SSPEN: Master Synchronous Serial Port Enable bit(2)
1= Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins
0= Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
1= Idle state for clock is a high level
0= Idle state for clock is a low level
bit 3-0
SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(3)
0101= SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin
0100= SPI Slave mode, clock = SCKx pin, SSx pin control enabled
0011= SPI Master mode, clock = TMR2 output/2
0010= SPI Master mode, clock = FOSC/64
0001= SPI Master mode, clock = FOSC/16
0000= SPI Master mode, clock = FOSC/4
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPxBUF register.
2: When enabled, these pins must be properly configured as input or output.
3: Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only.
© 2009 Microchip Technology Inc.
DS39682E-page 151
MICROCHIP [ MICROCHIP ]
