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PIC18F8620-I/PT 参数 Datasheet PDF下载

PIC18F8620-I/PT图片预览
型号: PIC18F8620-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器和处理器外围集成电路PC时钟
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18FXX20  
LFSR  
Load FSR  
MOVF  
Move f  
Syntax:  
[ label ] LFSR f,k  
Syntax:  
[ label ] MOVF f [,d [,a]  
Operands:  
0 f 2  
Operands:  
0 f 255  
d [0,1]  
a [0,1]  
f dest  
N, Z  
0 k 4095  
Operation:  
Status Affected:  
Encoding:  
k FSRf  
None  
1110  
1111  
Operation:  
Status Affected:  
Encoding:  
1110  
0000  
00ff  
k kkk  
11  
kkkk  
k kkk  
0101  
00da  
ffff  
ffff  
7
Description:  
The 12-bit literal 'k' is loaded into  
the file select register pointed to  
by 'f'.  
2
2
Description:  
The contents of register 'f' are  
moved to a destination dependent  
upon the status of ’d’. If 'd' is 0, the  
result is placed in W. If 'd' is 1, the  
result is placed back in register 'f'  
(default). Location 'f' can be any-  
where in the 256-byte bank. If ‘a’ is  
0, the Access Bank will be  
selected, overriding the BSR value.  
If ‘a’ = 1, then the bank will be  
selected as per the BSR value  
(default).  
Words:  
Cycles:  
Q Cycle Activity:  
Q1  
Q2  
Q3  
Q4  
Decode  
Read literal  
Process  
Write  
literal 'k'  
MSB to  
FSRfH  
'k' MSB  
Data  
Decode  
Read literal  
'k' LSB  
Process  
Data  
Write literal  
'k' to FSRfL  
Words:  
Cycles:  
1
1
Q Cycle Activity:  
Q1  
LFSR 2, 0x3AB  
Example:  
Q2  
Q3  
Q4  
Write W  
After Instruction  
Decode  
Read  
Process  
FSR2H  
FSR2L  
=
=
0x03  
0xAB  
register 'f'  
Data  
MOVF  
REG, 0, 0  
Example:  
Before Instruction  
REG  
W
=
=
0x22  
0xFF  
After Instruction  
REG  
W
=
=
0x22  
0x22  
2003 Microchip Technology Inc.  
Advance Information  
DS39609A-page 283  
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