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PIC18F8620-I/PT 参数 Datasheet PDF下载

PIC18F8620-I/PT图片预览
型号: PIC18F8620-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器和处理器外围集成电路PC时钟
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18FXX20  
INCFSZ  
Increment f, skip if 0  
INFSNZ  
Increment f, skip if not 0  
Syntax:  
[ label ] INCFSZ f [,d [,a]  
Syntax:  
[label] INFSNZ f [,d [,a]  
Operands:  
0 f 255  
d [0,1]  
a [0,1]  
Operands:  
0 f 255  
d [0,1]  
a [0,1]  
Operation:  
(f) + 1 dest,  
skip if result = 0  
Operation:  
(f) + 1 dest,  
skip if result 0  
Status Affected:  
Encoding:  
None  
0011  
Status Affected:  
Encoding:  
None  
0100  
11da  
ffff  
ffff  
10da  
ffff  
ffff  
Description:  
The contents of register 'f' are  
incremented. If 'd' is 0, the result is  
placed in W. If 'd' is 1, the result is  
placed back in register 'f'. (default)  
If the result is 0, the next instruc-  
tion, which is already fetched, is  
discarded, and a NOPis executed  
instead, making it a two-cycle  
instruction. If ‘a’ is 0, the Access  
Bank will be selected, overriding  
the BSR value. If ‘a’ = 1, then the  
bank will be selected as per the  
BSR value (default).  
Description:  
The contents of register 'f' are  
incremented. If 'd' is 0, the result is  
placed in W. If 'd' is 1, the result is  
placed back in register 'f' (default).  
If the result is not 0, the next  
instruction, which is already  
fetched, is discarded, and a NOPis  
executed instead, making it a  
two-cycle instruction. If ‘a’ is 0, the  
Access Bank will be selected, over-  
riding the BSR value. If ‘a’ = 1, then  
the bank will be selected as per the  
BSR value (default).  
Words:  
Cycles:  
1
1(2)  
Words:  
Cycles:  
1
1(2)  
Note: 3 cycles if skip and followed  
by a 2-word instruction.  
Note: 3 cycles if skip and followed  
by a 2-word instruction.  
Q Cycle Activity:  
Q1  
Q Cycle Activity:  
Q1  
Q2  
Q3  
Process  
Data  
Q4  
Q2  
Q3  
Process  
Data  
Q4  
Decode  
Read  
Write to  
Decode  
Read  
Write to  
register 'f'  
destination  
register 'f'  
destination  
If skip:  
Q1  
If skip:  
Q1  
Q2  
Q3  
Q4  
Q2  
Q3  
Q4  
No  
No  
No  
No  
No  
No  
No  
No  
operation  
operation  
operation  
operation  
operation  
operation  
operation  
operation  
If skip and followed by 2-word instruction:  
If skip and followed by 2-word instruction:  
Q1  
Q2  
No  
Q3  
No  
Q4  
Q1  
Q2  
No  
Q3  
No  
Q4  
No  
operation  
No  
No  
operation  
No  
operation  
operation  
operation  
operation  
operation  
operation  
No  
operation  
No  
operation  
No  
operation  
No  
operation  
No  
operation  
No  
operation  
No  
operation  
No  
operation  
HERE  
NZERO  
ZERO  
INCFSZ  
:
:
CNT, 1, 0  
HERE  
ZERO  
NZERO  
INFSNZ REG, 1, 0  
Example:  
Example:  
Before Instruction  
Before Instruction  
PC  
=
Address (HERE)  
PC  
=
Address (HERE)  
After Instruction  
After Instruction  
CNT  
If CNT  
PC  
=
=
=
=
CNT + 1  
REG  
If REG  
PC  
=
=
=
=
REG + 1  
0;  
0;  
Address (ZERO)  
0;  
Address (NZERO)  
0;  
If CNT  
PC  
If REG  
PC  
Address (NZERO)  
Address (ZERO)  
2003 Microchip Technology Inc.  
Advance Information  
DS39609A-page 281  
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