PIC18FXX20
TABLE 26-20: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
100
THIGH
Clock high time
100 kHz mode
4.0
—
—
µs
µs
PIC18FXX20 must operate
at a minimum of 1.5 MHz
PIC18FXX20 must operate
at a minimum of 10 MHz
400 kHz mode
0.6
SSP Module
100 kHz mode
1.5 TCY
4.7
—
—
101
TLOW
Clock low time
µs
µs
PIC18FXX20 must operate
at a minimum of 1.5 MHz
PIC18FXX20 must operate
at a minimum of 10 MHz
400 kHz mode
SSP Module
1.3
—
1.5 TCY
—
20 + 0.1 CB 300
—
1000
102
103
TR
TF
SDA and SCL rise 100 kHz mode
time
ns
ns
400 kHz mode
CB is specified to be from
10 to 400 pF
SDA and SCL fall 100 kHz mode
time
—
300
ns
ns
400 kHz mode
20 + 0.1 CB 300
CB is specified to be from
10 to 400 pF
90
TSU:STA
THD:STA
START condition
setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
—
—
—
0.9
—
—
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Only relevant for Repeated
START condition
91
START condition
hold time
After this period, the first
clock pulse is generated
106
107
92
THD:DAT Data input hold
time
0
TSU:DAT
TSU:STO
TAA
Data input setup
time
250
100
4.7
0.6
—
—
4.7
1.3
(Note 2)
STOP condition
setup time
109
110
Output valid from
clock
3500
—
—
(Note 1)
TBUF
Bus free time
Time the bus must be free
before a new transmission
can start
—
D102
CB
Bus capacitive loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement
TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the
LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line.
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before
the SCL line is released.
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 335
MICROCHIP [ MICROCHIP ]
