PIC18FXX20
FIGURE 26-19:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
bit6 - - - - - -1
bit6 - - - -1
LSb
SDO
SDI
75, 76
77
MSb In
74
LSb In
Note: Refer to Figure 26-6 for load conditions.
TABLE 26-18: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param.
Symbol
Characteristic
Min
Max Units Conditions
No.
70
TssL2scH, SS ↓ to SCK ↓ or SCK ↑ input
TCY
—
ns
TssL2scL
71
71A
72
72A
73A
74
TscH
TscL
TB2B
SCK input high time
(Slave mode)
SCK input low time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
40
1.25 TCY + 30
40
(Note 1)
(Note 1)
(Note 2)
Last clock edge of Byte1 to the first clock edge of Byte2 1.5 TCY + 40
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
75
TdoR
TdoF
SDO data output rise time
SDO data output fall time
PIC18FXX20
PIC18LFXX20
—
25
45
25
50
25
45
25
50
100
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
76
77
78
—
10
—
—
—
—
—
—
—
TssH2doZ SS ↑ to SDO output hi-impedance
TscR
SCK output rise time
(Master mode)
SCK output fall time (Master mode)
PIC18FXX20
PIC18LFXX20
79
80
TscF
TscH2doV, SDO data output valid after SCK PIC18FXX20
TscL2doV edge
TssL2doV SDO data output valid after SS ↓ PIC18FXX20
PIC18LFXX20
82
83
edge
PIC18LFXX20
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5 TCY + 40
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 333
MICROCHIP [ MICROCHIP ]
