PIC18FXX20
FIGURE 26-17:
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
LSb
MSb
bit6 - - - - - -1
bit6 - - - -1
SDO
SDI
75, 76
MSb In
74
LSb In
Note: Refer to Figure 26-6 for load conditions.
TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
Symbol
TscH
Characteristic
Min
Max Units Conditions
No.
71
71A
72
72A
73
SCK input high time
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
ns
ns
ns
ns
(Slave mode)
40
1.25 TCY + 30
40
(Note 1)
(Note 1)
TscL
SCK input low time
(Slave mode)
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
TB2B
100
—
—
—
ns
ns
ns
73A
74
Last clock edge of Byte1 to the 1st clock edge
of Byte2
1.5 TCY + 40
(Note 2)
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
TdoR
100
—
75
SDO data output rise time
SDO data output fall time
PIC18FXX20
PIC18LFXX20
25
45
25
25
45
25
50
100
ns
ns
ns
ns
ns
ns
ns
ns
76
78
TdoF
TscR
—
—
SCK output rise time
PIC18FXX20
PIC18LFXX20
(Master mode)
79
80
TscF
SCK output fall time (Master mode)
—
—
TscH2doV, SDO data output valid after
TscL2doV SCK edge
PIC18FXX20
PIC18LFXX20
81
TdoV2scH, SDO data output setup to SCK edge
TdoV2scL
TCY
—
ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 331
MICROCHIP [ MICROCHIP ]
