PIC18FXX20
FIGURE 26-22:
MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS
SCL
SDA
93
91
90
92
STOP
Condition
START
Condition
Note: Refer to Figure 26-6 for load conditions.
TABLE 26-21: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
90
TSU:STA START condition
Setup time
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for
Repeated START
condition
1 MHz mode(1) 2(TOSC)(BRG + 1)
91
92
93
THD:STA START condition
Hold time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
ns After this period, the
first clock pulse is
generated
TSU:STO STOP condition
Setup time
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
ns
THD:STO STOP condition
Hold time
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
ns
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
FIGURE 26-23:
MASTER SSP I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
91
92
107
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 26-6 for load conditions.
DS39609A-page 336
Advance Information
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
