PIC18CXX2
When TMR1CS = 0, Timer1 increments every instruc-
tion cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input or the
Timer1 oscillator, if enabled.
10.1
Timer1 Operation
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
Timer1 also has an internal “reset input”. This reset can
be generated by the CCP module (Section 13.0).
FIGURE 10-1: TIMER1 BLOCK DIAGRAM
CCP Special Event Trigger
TMR1IF
Overflow
Interrupt
Synchronized
TMR1
0
Clock Input
CLR
TMR1L
Flag Bit
TMR1H
T1OSC
1
TMR1ON
on/off
T1SYNC
1
0
T1CKI/T1OSO
T1OSI
Synchronize
det
T1OSCEN
Enable
Oscillator
Prescaler
1, 2, 4, 8
FOSC/4
(1)
Internal
Clock
2
SLEEP input
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This
eliminates power drain.
FIGURE 10-2: TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data bus<7:0>
8
TMR1H
8
8
Write TMR1L
Read TMR1L
Synchronized
0
TMR1IF
Overflow
Interrupt
TMR1
8
clock input
Timer 1
high byte
TMR1L
flag bit
1
TMR1ON
on/off
T1SYNC
T1OSC
T13CKI/T1OSO
T1OSI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Oscillator
Fosc/4
Internal
Clock
0
(1)
2
SLEEP input
TMR1CS
T1CKPS1:T1CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates
power drain.
DS39026B-page 98
Preliminary
7/99 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
