PIC18CXX2
Register 7-7: Peripheral Interrupt Priority Registers
R/W-1
PSPIP
R/W-1
ADIP
R/W-1
RCIP
R/W-1
TXIP
R/W-1
SSPIP
R/W-1
R/W-1
R/W-1
IPR1
CCP1IP TMR2IP TMR1IP
bit 7
bit 0
U-0
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
IPR2
IPR1
—
—
—
—
BCLIP
LVDIP
TMR3IP CCP2IP
bit 7
bit 0
bit 7
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit
1= High priority
0= Low priority
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ADIP: A/D Converter Interrupt Priority bit
1= High priority
0= Low priority
RCIP: USART Receive Interrupt Priority bit
1= High priority
0= Low priority
TXIP: USART Transmit Interrupt Priority bit
1= High priority
0= Low priority
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1= High priority
0= Low priority
CCP1IP: CCP1 Interrupt Priority bit
1= High priority
0= Low priority
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1= High priority
0= Low priority
TMR1IP: TMR1 Overflow Interrupt Priority bit
1= High priority
0= Low priority
IPR2
bit 7-4
bit 3
Unimplemented: Read as '0'
BCLIP: Bus Collision Interrupt Priority bit
1= High priority
0= Low priority
bit 2
bit 1
bit 0
LVDIP: Low-voltage Detect Interrupt Priority bit
1= High priority
0= Low priority
TMR3IP: TMR3 Overflow Interrupt Priority bit
1= High priority
0= Low priority
CCP2IP: CCP2 Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
- n = Value at POR reset
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
DS39026B-page 74
Preliminary
7/99 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
