PIC18C452-I/L 参数 Datasheet PDF下载

型号：	PIC18C452-I/L
PDF下载：	下载PDF文件查看货源
内容描述：	高性能微控制器，10位A / D [High-Performance Microcontrollers with 10-Bit A/D]
分类和应用：	微控制器
文件页数/大小：	296 页 / 4835 K
品牌：	MICROCHIP [ MICROCHIP ]

PIC18CXX2

TABLE 3-3:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.’d)

MCLR Resets

WDT Reset

Power-on Reset,

Brown-out Reset

Reset Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Applicable Devices

ADRESH

ADRESL

ADCON0

ADCON1

CCPR1H

CCPR1L

242 442 252 452

xxxx xxxx

0000 0000

--0- 0000

xxxx xxxx

--00 0000

xxxx xxxx

--00 0000

xxxx xxxx

0000 0000

xxxx xxxx

0000 -01x

0000 000x

---- 1111

---- 0000

uuuu uuuu

0000 0000

--0- 0000

uuuu uuuu

--00 0000

uuuu uuuu

--00 0000

uuuu uuuu

0000 -01u

0000 000u

---- 1111

---- 0000

uuuu uuuu

--u- uuuu

uuuu uuuu

--uu uuuu

uuuu uuuu

--uu uuuu

uuuu uuuu

uuuu -uuu

uuuu uuuu

---- uuuu

CCP1CON 242 442 252 452

CCPR2H

CCPR2L

242 442 252 452

CCP2CON 242 442 252 452

TMR3H

TMR3L

T3CON

SPBRG

RCREG

TXREG

TXSTA

RCSTA

IPR2

242 442 252 452

---- uuuu⁽¹⁾

---- uuuu

uuuu uuuu

-uuu uuuu

PIR2

PIE2

IPR1

242 442 252 452

---- 0000

1111 1111

-111 1111

0000 0000

---- 0000

1111 1111

-111 1111

0000 0000

uuuu uuuu⁽¹⁾

PIR1

PIE1

-uuu uuuu⁽¹⁾

uuuu uuuu

-uuu uuuu

242 442 252 452

-000 0000

242 442 252 452

0000 0000

-000 0000

0000 0000

-000 0000

Legend: u = unchanged, x = unknown, -= unimplemented bit, read as ’0’, q = value depends on condition

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-

ware stack.

4: See Table 3-2 for reset value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other

oscillator modes, they are disabled and read ’0’.

6: The long write enable is only reset on a POR or MCLR reset.

7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’.

DS39026B-page 28

Preliminary

7/99 Microchip Technology Inc.

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